module ctrl (
  input  [31:0] instr,
  output branch,
  output mem_to_reg,
  output [1:0] alu_op,
  output mem_write,
  output alu_src,
  output reg_write,
  output [2:0] imm_ctrl
);
  // output mem_read,

  wire [6:0] opcode;
  
  assign opcode = instr[6:0];

  assign branch = opcode[6];
  // assign mem_read    = (~opcode[6]) & (~opcode[5]) & (~opcode[4]);
  assign mem_to_reg  = (~opcode[6]) & (~opcode[5]) & (~opcode[4]);
  assign alu_op[0]   = ( opcode[6]) & ( opcode[5]) & (~opcode[4]);
  assign alu_op[1]   = (~opcode[6]) & ( opcode[4]);
  assign mem_write   = (~opcode[6]) & ( opcode[5]) & (~opcode[4]);
  assign alu_src     = (~opcode[6]) & (~(opcode[5] &  opcode[4]));
  assign reg_write   = (~opcode[6]) & (~(opcode[5] & ~opcode[4]));
  assign imm_ctrl[0] = opcode[5];
  assign imm_ctrl[1] = opcode[6];
  assign imm_ctrl[2] = 0;

endmodule